verilog 顶层模块的实例

比如工程名为converter,顶层文件名为converter.v,子模块为sw.v,顶层文件架构为:
module converte(reset,dte_xtc,mclk,rclk,cable_sel,code_sel,clk_sel,cts_s,dte_rts,llb,rlb,rcl,tclk,ets,rt,l,loop,hbe,ctso,dsro,dcdo,tst_led);
input reset,dte_xtc,mclk,rclk,cable_sel,code_sel,cts_s,dte_rts,llb,rlb,rcl,ets;
input [1:0]clk_sel;
output [1:0]rt,loop;
output [2:0]l;
output tclk,hbe,ctso,dsro,dcdo,tst_led;


sw dut_1(reset,dte_xtc,mclk,rclk,cable_sel,code_sel,clk_sel,cts_s,dte_rts,llb,rlb,rcl,tclk,ets,rt,l,loop,hbe,ctso,dsro,dcdo,tst_led);

endmodule


子模块架构为:
module sw(reset,dte_xtc,mclk,rclk,cable_sel,code_sel,clk_sel,cts_s,dte_rts,llb,rlb,rcl,tclk,ets,rt,l,loop,hbe,ctso,dsro,dcdo,tst_led);
input reset,dte_xtc,mclk,rclk,cable_sel,code_sel,cts_s,dte_rts,llb,rlb,rcl,ets;
input [1:0]clk_sel;
output [1:0]rt,loop;
output [2:0]l;
output tclk,hbe,ctso,dsro,dcdo,tst_led;
reg [1:0]rt,loop;
reg[2:0]l;
reg tclk,hbe,ctso,dsro,dcdo,tst_led;
......

......
endmodule

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